1. Field of the Invention
The invention relates to simulation tools, and particularly to storing detailed deviation information from a simulated layout, thereby facilitating flexible and dynamic reporting capability.
2. Discussion of the Related Art
In sub-wavelength designs, traditional design rule checking (DRC) tools cannot be relied upon as a final check for silicon manufacturability. Specifically, because features can be distorted during the sub-wavelength manufacturing process due to both local and global proximity effects, DRC tools cannot provide the coverage and assurance needed for silicon sign-off.
To resolve this problem, certain simulation tools have been provided that can verify the layout of a sub-wavelength integrated circuit compared to the printed wafer. Numerical Technologies, Inc. licenses such a tool, the SiVL® software package. This simulation tool can read in a user's layout and then simulate lithographic processes and conditions. The resulting simulated wafer image can be compared to the user's layout.
Prior to this comparison step, the user is generally prompted to designate a tolerance, i.e. a maximum acceptable deviation, from the user's original layout. In one embodiment, the simulation tool can generate a graphical output including the original layout with contours showing the simulated wafer image. An area of the layout exceeding the tolerance can be marked with a graphical symbol, such as a “+” or “▪”. See, for example, U.S. patent application Ser. No. 09/960,669, filed on Sep. 21, 2001 by Numerical Technologies, Inc. Understanding where tolerance violations occur can indicate problems with the design or perhaps errors in providing rule parameters. However, setting a zero-tolerance can result in a large number of tolerance violations throughout the layout. Thus, setting the tolerance too tight generates too much information for a useful user review. Moreover, the appropriate tolerance can vary significantly from one design to another design. Therefore, determining an appropriate tolerance that can provide useful simulation results is frequently a trial and error process.
Unfortunately, a new tolerance cannot leverage the results of a previous simulation. Specifically, setting a new tolerance requires repeating the simulation, thereby wasting considerable resources. For example, a medium-sized integrated circuit layout may take between 12 and 24 hours to simulate. Thus, the simulation tool is inefficiently used to re-run simulations on the same design rather than running new designs. Moreover, after this long process time, the user analysis done for proposing that specific tolerance may not be retained, thereby requiring further analysis. Thus, user time is also wasted on one design.
Therefore, a need arises for minimizing inefficient resource allocation by improving the simulation process. A further need arises for providing flexible and dynamic reporting capability to the user.